In semiconductor integrated circuits, output buffer circuits are generally used to output an internal data via an output terminal such as, an output pad. As the interface grows up, output drivers have been an important component for high quality signals integrity, because the output voltage levels and a slew rate are mainly determined by the output drivers.
The operating characteristics of CMOS transistors, from which the drivers are constructed, change under a variety of conditions, often referred to as process, voltage and temperature (PVT) variations. The PVT variations may be conceptualized as a box across, which the operating characteristics of the transistors move. For example, the operating characteristics may move from a fastest corner of the PVT variations to a slowest corner of the PVT variations, and everywhere in between. If inadequate compensation is made for these variations, an output slew rate may vary substantially within a particular driver as well as from a driver to a driver on a chip.
To achieve good signal integrity, the variations in an output current slew rate must be minimized over the PVT variations. A large slew rate induces much switching noise, (L*di/dt) noise, and a small slew rate decrease the signal timing margin. In a conventional output slew rate control scheme, a pre-driver is set to a fixed value, so the time constant (RC) of a pre-driver node determines the output slew rate. But, if PVT conditions vary, the time constant becomes different, so the slew rate goes far from its optimal values.
FIG. 1 describes a schematic circuit diagram of a conventional split-gate output driver. The output buffer includes a pull-up PMOS transistor P11 and a pull-down NMOS transistor N11; two pre-driver sections (slew rate control sections) to individually control each driver's transistor during output transitions viz. a first inverter 104 that inverts an output data A, applies an inverted output data to a gate of the pull-up transistor P11, and controls the pull-up slew rate of an output driver 102; and a second inverter 106 that applies the inverted output data to a gate of the pull-down transistor N11, and controls the pull-down slew rate of the output driver 102.
In the output buffer circuit of the FIG. 1, the pull-up slew rate of the output driver 102 is determined based on a current flow charging the load capacitance of an output terminal PAD through the pull-up transistor P11 and the fall time of the pre-driver node PD, which in turn is controlled by a current of the NMOS transistor N12. Similarly, the pull-down slew rate of the output driver 102 is determined based on a current flow discharging the load capacitance of an output terminal PAD through the pull-down transistor N11 and the fall time of the pre-driver node ND, which in turn is controlled by the current of PMOS transistor P13.
These currents, which affect the slew rate of the output driver 102 varies considerably in the presence of PVT variations on a chip. Accordingly, the slew rate of the output driver 102 also varies considerably in the presence of PVT variations. The conventional output buffer circuit as, explained in the FIG. 1, it is difficult to maintain the slew rate within a narrow tolerance under conditions in which the PVT may vary.
Therefore, there is a need for a novel circuit and method for providing an improved slew rate control over process, voltage and temperature (PVT) conditions.